Logical AND
Organizational graphic tag to help group instructions

Mnemonic

 AND

Short and Long format of instruction



Description

The contents of the accumulator are ANDed, bit by bit, with the contents of the addressed core storage location. The result replaces the contents of the accumulator. ANDing occurs only between corresponding bit positions in the accumulator and the core-storage word: bit 0 is ANDed only with bit 0, bit 1 only with bit 1, and so on. The four possible ANDing results are:


Bit Values  
From Core Storage Word From Accumulator Result in Accumulator
0 0 0
0 1 0
1 0 0
1 1 1

Contents of the addressed core-storage word are not changed as a result of the operation. An example of ANDing is:

    0101 0000 1111 1010    Word in accumulator
AND 1010 1111 1010 1111    Word from core storage
    0000 0000 1010 1010    Result in accumulator

There are no addressing exceptions for the logical AND instruction; all forms of addressing that are described under "Effective-Address Generation" apply to the AND instruction.


Indicators: The carry and overflow indicators are not affected during the AND operation.


Programming Note: The AND instruction is particularly useful in two applications.


  1. It can be used to set a specific bit off as: 
        XXXX XXXX XXXX XXXX Word in accumulator
AND 1111 1101 1111 1111 Mask in storage
    XXXX XXOX XXXX XXXX Result in accumulator
  2. It can be used to isolate a bit for testing as: 
        XXXX XXXX XXXX XXXX Word in accumulator
AND 0001 0000 0000 0000 Mask in storage
    O00X 0000 0000 0000 Result in accumulator

Examples

Logical AND

Assembler Language Coding Hexadecimal Value Description of Instruction
Label   Operation   F T    
21 25
  
27 30
   32 33   35..40..
    AND         DISP E0XX AND contents of CSL at EA (I+DISP) with A
    AND     1   DISP E1XX AND contents of CSL at EA (XR1+DISP) with A
    AND     2   DISP E2XX AND contents of CSL at EA (XR2+DISP) with A
    AND     3   DISP E3XX AND contents of CSL at EA (XR3+DISP) with A
    AND   L     ADDR E400XXXX AND contents of CSL at EA (Addr) with A
    AND   L 1   ADDR E500XXXX AND contents of CSL at EA (Addr+XR1) with A
    AND   L 2   ADDR E600XXXX AND contents of CSL at EA (Addr+XR2) with A
    AND   L 3   ADDR E700XXXX AND contents of CSL at EA (Addr+XR3) with A
    AND   I     ADDR E480XXXX AND contents of CSL at EA (V in CSL at Addr) with A
    AND   I 1   ADDR E580XXXX AND contents of CSL at EA (V in CSL at "Addr+XR1") with A
    AND   I 2   ADDR E680XXXX AND contents of CSL at EA (V in CSL at "Addr+XR2") with A
    AND   I 3   ADDR E780XXXX AND contents of CSL at EA (V in CSL at "Addr+XR3") with A

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