Synchronous Communications Adapter



The synchronous communications adapter special feature enables the IBM 1130 Computing System to function as a point-to-point station or multipoint data transmission terminal, using either private or commercial common-carrier (switched or non-switched) line transmission facilities. The adapter sends data to or receives data from the line transmission facilities under control of the stored program in the 1130. It operates on an interrupt request basis similar to that used by other input/output devices in the IBM 1130 Computing System.

The synchronous communications adapter (SCA) provides data interchange between remote locations and a central data-processing location. The mode of communication may be either binary synchronous or synchronous transmit-receive and requires its own program. The mode is switch-selected by the operator. IBM supplies subroutines to support both modes.

The term "synchronous transmission" is used to describe continuous bit-stream transmission, without start-of-character identification. Thus, synchronous transmission is more efficient than start/stop transmission because fewer control bits are transmitted.

Binary Synchronous Communications (BSC)

The binary synchronous mode of data transmission provides for point-to-point and multipoint operation. The 1130 may be the primary station in a communication network or it may serve as a secondary station to a larger computing system. IBM programming systems provide primary and secondary station support for point-to-point operation and secondary station support for multipoint operation.

The capability of BSC mode to operate with any six-, seven-, or eight-bit level code provides the 1130 with the ability to communicate with a greater variety of devices. It is no longer necessary for a device to adhere to an eight-bit level code in order to communicate with the 1130 system.

Certain factors should be considered in selecting a character set if the user does not use the IBM-supported character sets. The six- and seven-bit codes provide a faster and more efficient type of communication because the data sets are rated in bits per second. Thus, the fewer number of bits to make a character, the more characters may be transmitted in any given segment of time. However, the number of separate characters that can be contained in a code is decreased, proportionately, as the number of bits used to make a character is decreased.

IBM programming systems support for the SCA in the BSC mode includes a subroutine for point-to-point operation and a subroutine for multipoint operation of a secondary station. Using these programs, text may be transmitted in either normal text (extended binary-coded-decimal interchange code, System/360 and 1130 internal code) or full-transparent text. Full-transparent text uses EBCDIC communication control characters. In normal text, data may not have the same bit configuration as any control character. In full-transparent text, control character recognition is handled by a special procedure, thus making it possible to have data with the same configuration as control characters. Full-transparent text permits unrestricted coding of data within messages, and is useful in transmitting binary data, decimal data, and other data configurations.

A 2701 or 2703 Data Transmission Unit with the binary synchronous feature (SDA-2) must be attached to System/360 Models 30, 40, 50, 65, and 75 for communication in the BSC mode.

Synchronous Transmit-Receive (STR)

All synchronous transmit-receive (STR) devices use the four-of-eight line transmission code shown in Figure 71. The STR mode provides only point-to-point communication. It is used to communicate with the IBM 1009 Data Transmission Unit, the IBM 7701 and 7702 Magnetic Tape Transmission Terminals, the IBM 1013 Card Transmission Terminal, the IBM 7710 and 7711 Data Communication Units, and other STR devices.

The SCA provides the 1130 system with the ability to communicate with the communications adapter (#2073) of the Model 20 and with other System/360 configurations which have the IBM 2701 Data Transmission Unit attached. System/360 (other than Model 20) in the STR mode requires a 2701 (with the SDA-1 feature) attached to System/360.

LINE ATTACHMENT

The synchronous communications adapter is attached to either private or commercial line transmission facilities through a common-carrier data set. In the United States the interface for this data set is defined by ETA (Electronic Industries Association) Standard RS-232-B (voltage mode) and requires a Western Electric data set model 201A3, 201A4, 201B1, 201B2, 202C1, 202D1, or equivalent. Outside the United States the data set is defined by the CCITT (Consultive Committee on International Telephone and Telegraph) Standard and requires an IBM 3977 Modem or equivalent.

Graphic 4 of 8 Code   Graphic 4 of 8 Code
N X O R  8 4 2 1 N X O R  8 4 2 1
blank 1 1 1 1  0 0 0 0* F 0 1 1 0  0 1 1 0
¢ 0 1 1 0  1 0 1 0 G 1 0 0 0  0 1 1 1
. 1 0 0 0  1 0 1 1 H 0 1 1 1  1 0 0 0
< 0 1 1 0  1 1 0 0 I 0 1 1 0  1 0 0 1
( 0 1 0 1  0 1 1 0 J 1 1 0 1  0 0 0 1
+ 0 0 1 1  0 1 1 0 K 1 1 0 1  0 0 1 0
|** 1 0 0 0  1 1 0 1 L 1 1 0 0  0 0 1 1
& 1 0 0 0  1 1 1 0 M 1 1 0 1  0 1 0 0
! 1 1 0 0  1 0 1 0 N 1 1 0 0  0 1 0 1
$ 0 1 0 0  1 0 1 1 O 1 1 0 0  0 1 1 0
* 1 1 0 0  1 1 0 0 P 0 1 0 0  0 1 1 1
) 0 1 0 1  1 1 0 0 Q 1 1 0 1  1 0 0 0
; 0 0 1 1  1 1 0 0 R 1 1 0 0  1 0 0 1
¬ 0 1 0 0  1 1 0 1 none# 1 0 1 0  1 0 1 0
- 0 1 0 0  1 1 1 0 S 1 0 1 1  0 0 1 0
/ 1 0 1 1  0 0 0 1 T 1 0 1 0  0 0 1 1
, 0 0 1 0  1 0 1 1 U 1 0 1 1  0 1 0 0
% 1 0 1 0  1 1 0 0 V 1 0 1 0  0 1 0 1
_ 0 1 0 1  1 0 1 0 W 1 0 1 0  0 1 1 0
> 0 0 1 1  1 0 1 0 X 0 0 1 0  0 1 1 1
? 0 0 1 0  1 1 0 1 Y 1 0 1 1  1 0 0 0
: 0 0 1 0  1 1 1 0* Z 1 0 1 0  1 0 0 1
# 0 0 0 1  1 0 1 1 0 1 0 0 1  1 0 1 0
@ 1 0 0 1  1 1 0 0 1 1 1 1 0  0 0 0 1
' 0 0 0 0  1 1 1 1 2 1 1 1 0  0 0 1 0
= 0 0 0 1  1 1 1 0 3 1 0 0 1  0 0 1 1
" 0 0 0 1  1 1 0 1 4 1 1 1 0  0 1 0 0
A 0 1 1 1  0 0 0 1 5 1 0 0 1  0 1 0 1
B 0 1 1 1  0 0 1 0 6 1 0 0 1  0 1 1 0
C 0 1 1 0  0 0 1 1 7 0 0 0 1  0 1 1 1
D 0 1 1 1  0 1 0 0 8 1 1 1 0  1 0 0 0
E 0 1 1 0  0 1 0 1 9 1 0 0 1  1 0 0 1
*This is correct for System/360 Programs, but is not consistent with certain other STR devices.
**Group Mark
#Record Mark

Figure 71. STR 4-of-8 Line Transmission Code



The SCA can operate in half-duplex mode using either two-wire or four-wire line transmission facilities. Data rates, selected by the machine operator, are 600, 1200, 2000, or 2400 baud (bits per second) in STR or BSC mode. In BSC mode only, operation can be at 4800 baud.

The adapter can be jumper wired to allow the program to control the data terminal ready condition in the data set interface. This selection will allow the program to control the disconnect of a switched data link. If the program-controlled disconnect feature is used, any such disconnect will prevent further operations with the data set until the communication adapter is restored to transmit mode, receive mode, or auto-answer enabled condition.

Half-Duplex Operation

Half duplex is a mode of operation wherein either terminal can transmit or receive in conjunction with the remote terminal, but neither terminal can transmit and receive data simultaneously. In effect, the operation is quite similar to a normal telephone conversation; that is, one party talks while the other party listens. During the course of the conversation, each party may alternate between talking and listening as often as necessary.


Two-Wire Operation

Synchronous transmit-receive or binary synchronous operation with a two-wire half-duplex transmission system requires a delay of approximately 200 milliseconds when the adapter switches from receiving to transmitting data. This turnaround delay allows the data set and the communication lines to reverse the direction of transmission and line echo to settle. The amount of delay is therefore related to the character of the line and data set. Line turnaround time is controlled by the data set. When this turnaround is completed, the data set signals the adapter. The adapter does not transmit until the data set signals the completion of line turnaround by activating the clear-to-send (CTS) line.


Four-Wire Operation

The adapter operates in four-wire mode with either half- or full-duplex communications facility. Four-wire, half-duplex operates the same as two wire. That is, request-to-send is controlled by the adapter. The advantage of this facility is that the 200-ms delay on turnaround is saved.

STR operation in a four-wire, full-duplex facility requires that idle characters be transmitted on the pair of wires that is not passing intelligent data. This allows the STR adapter or STR device to maintain character phase and receive-clock synchronism.

BSC operation on a four-wire, full-duplex facility eliminates turnaround time. Unlike STR, the pair of wires that is not being used at any given time does not pass idle on SYN characters. BSC mode does not maintain continuous clock synchronization but requires that the clocks be re-synchronized each time the adapter is turned around.

FUNCTIONAL DESCRIPTION

The entire synchronous communications adapter is contained within the 1131 Central Processing Unit. The adapter functions as an input/output control unit between the 1130 system and the transmission line. All data transfer is character-synchronous. This means that once an initial synchronous idle character is recognized, each subsequent character is recognized as a group of incoming data bits timed by an internal electronic clock for data terminal clocking or by the data set clock for data set clocking. Continuous regulation of the receiver's clock is provided in the case of data terminal clocking.

Incoming data from the transmission line is serial by bit and serial by character. As the data comes in, it is stored, one bit at a time, in the receive deserializer. When a complete character has been assembled, the character is transferred into the buffer register. Then the adapter initiates an interrupt request to notify the CPU that a character is ready to be read into core storage. When the interrupt request is serviced, the character is read in parallel into the high-order eight positions of a 16-bit word in core storage.

Outgoing data, from core storage to the transmission line, is taken in parallel from the high-order eight positions of the address location in core storage. The adapter initiates an interrupt request to notify the CPU that the adapter is ready to accept a character from core storage. When the interrupt request is serviced, the character is transferred in parallel to the adapter buffer register. Data from the register is subsequently sent to the transmission line one bit at a time.

Data transfer to or from the transmission line begins with the low order position. Each eight-bit character is located in bit positions 0-7 of a 16-bit core storage location as follows:

Bit Transfer Sequence   Bit Position in Core Storage
First   7
Second   6
Third   5
Fourth   4
Fifth   3
Sixth   2
Seventh   1
Eighth   0

The seventh and eighth (bit 6 and 7) bits are ignored when using a six-bit level code. The eighth bit (bit 7) is ignored when using a seven-bit level code (Figure 72).

Timers

There are three electronic timers in the SCA. Each timer is adjustable. One timer is set for 3 seconds and another is set for 1.25 seconds. The third timer (0.35 seconds) is available for sync insertions in transparent mode, BSC.

In the STR mode the three-second timer is designated as the receive timer and causes an interrupt and turns on DSW bit 3 when in the receive mode to signal the end of the listening period while establishing synchronization. This interrupt also occurs in the transmit mode if a clear to send is not received from the data set within a three-second period. Clear to send is a signal from the data set when it is ready.

The 1.25-second timer is used in the synchronize mode to signal the end of the transmission of idle characters for synchronization in the STR mode. It also causes an interrupt with DSW bit 3 on. This timeout is always coincident with a write response.

The third timer is inhibited in STR operation.

An XIO control (100) command with bit 10 on turns on a timer trigger which inhibits the 1.25- and 3-second timers when it is first issued. Issuing the command a second time removes the inhibited status, leaving the timers free to run. This command reverses the status of the timers each time it is issued.

The timers may be restarted at any time by issuing a sense device (111) command with bit 14 on if they are not inhibited.

In the BSC mode, the timers are set the same as for STR, but they have a different function. The receive timer (3 seconds) starts to run when the program enters the receive mode. The program should restart this timer when it detects the synchronous idle sequence (Figure 76). The sending station must transmit this sequence every 1.25 seconds. The 3-second timer also interrupts in the transmit mode if a clear to send is not received from the data set within 3 seconds. In either case DSW bit 3 is turned on.

The 1.25-second timer is used in the synchronize mode to signal the program that it is time to transmit the synchronous idle sequence.

The third timer (designated the program timer) will interrupt in either transmit or receive mode if it is allowed to run by the timer trigger. The IBM-supplied subroutines use this timer and therefore it is not available for customer use when these subroutines are used.

Figure 72. Communication Data Flow
Figure 72. Communication Data Flow

An XIO control (100) command with bit 10 on inhibits the 1.25- and 3-second timers and starts the program timer. If the program timer is allowed to time out it resets the timer trigger and removes the inhibit condition from the other timers. Issuing another control command with bit 10 on also resets the timer trigger. A sense device (111) command with bit 14 on will restart any timer that is running.

Synchronous Transmit-Receive (STR) Operation

In order to communicate with a STR device, the STR/BSC switch msut be placed in the STR position, and the 1130 must contain a program to control the communication. The program must use the four-of-eight code and must use STR line-control conventions. IBM provides a subroutine to control STR communication. This program is described in IBM 1130 SCA Subroutines , Order No. GC26-3706.

STR line-control conventions are described below. Most of the operations described are performed automatically when the IBM subroutine is used. These operations are described here for the user that wishes to write his own routines, and to provide a general understanding of STR communication.

IBM programming systems support for the SCA in the STR mode of operation uses the four-of-eight code. Two types of characters are used:

  1. Control characters are used to control line functions; i.e., to acknowledge receipt of a message, to acknowledge synchronization, to signal the start of a message or the end of a transmission. The four-of-eight code, used by STR devices, contains special characters used to control line functions.
  2. Data characters contain the information to be transferred to or from the adapter. The four-of-eight code contains 64 valid data characters; however, some STR devices do not utilize all of the 64 data characters. The 1130 system can recognize any or all of the 64 data characters as directed by the stored program, but the programmer should determine the character set recognized by the remote STR to avoid sending invalid characters.
Control Operations — STR

The four-of-eight code contains special characters which are reserved for control functions. These control characters and their bit structures are shown in Figure 73. Control sequences are initiated by the 1130 program and are transmitted to the remote terminal as data. The remote terminal then has the responsibility of recognizing the control sequence and responding appropriately.

All operations of the adapter are controlled by the 1130 program. The program places the adapter in either the synchronize, transmit, or receive mode. In addition the program must initially store the idle character in the sync/idle register and must generate the longitudinal redundancy check (LRC) character, which is transmitted at the end of each record.

The idle character is a special character which the adapter transmits automatically to the receiving terminal when no other data or control characters have been transferred to the adapter for transmission. This condition occurs during the synchronization mode at the start of each transmission, and when the program responds too slowly to the adapters [sic] request data. The idle character is not included in the LRC character. At least one idle character must be transmitted before each block of records. The adapter makes this transmission automatically on line turnaround.

Control characters are used generally in two-character sequences (Figure 74). Each sequence is made up of a leader character and a trailer character. Two of the control characters can be used as leaders of a control sequence. These are the transmit leader (TL) character and the control leader (CL) character. The special characters used as trailers each have two possible meanings depending on whether the TL or the CL character precedes them. For example, the INQ/ERR character is interpreted as an INQ character when preceded by the TL leader and is interpreted as an ERR character when preceded by the CL leader. The end-of-transmission sequence and the telephone sequence consist of one control character followed by one of two data characters. These data characters are interpreted as being part of a control sequence only when they are preceded by the CL character. When not preceded by the CL character, they are interpreted as data.

The inquiry control sequence is used by a terminal when it wishes to transmit a message. The terminal that is in control status may at any time send the inquiry control sequence, which notifies the other terminal of the desire to transmit and asks for permission to do so. If the other terminal is able to receive a message, it acknowledges the inquiry control sequence with an acknowledge sequence.

The start-of-record control sequence is transmitted immediately before each block of data. The start-of-record 1 (SOR 1) control sequence is transmitted before the first, third, fifth, etc., record of each message, while the start-of record-2 (SOR 2) control sequence is transmitted before the second, fourth, sixth, etc., record of each message. This odd-even labeling of each record is used to ensure that no records of a message are lost or duplicated.

The end-of-transmittal record control sequence is sent immediately after each record of a message. The end-of-transmittal record control sequence contains the LRC character, which is used to check the validity of the transmission.


Control Characters 4 of 8 Code
N X O R 8 4 2 1
Buffer Positions 0 1 2 3 4 5 6 7
Idle 0 0 1 1 1 0 0 1
Start of Record 1 or Acknowledge 1
(SOR 1 or ACK 1)
0 1 0 1 0 0 1 1
Start of Record 2 or Acknowledge 2
(SOR 2 or ACK 2)
0 0 1 1 0 0 1 1
Transmit Leader (TL) 0 0 1 1 0 1 0 1
Control Leader (CL) 0 1 0 1 0 1 0 1
End of Transmission (EOT)* 0 1 0 1 1 0 1 0
Inquiry or Error (INQ or ERR) 0 1 0 1 1 0 0 1
Telephone* 0 1 0 1 1 1 0 0
Group Mark 1 0 0 0 1 1 0 1
Longitudinal Redundancy Check (LRS)** - - - - - - - -
* Also used as a data character
** This character has a 0 bit in each position that contained an
even number of 1 bits for that bit position in the data record. If
that bit position in the record had an odd number of 1 bits the
LRC character ranges from all 0s to all 1s and thus, is not in the
4 of 8 code.

Figure 73. STR Control Characters

One of the acknowledge control sequences is sent by the receiving terminal after it correctly receives each block of data. This control sequence indicates to the transmitting terminal that it may proceed to send another record. The acknowledge record 1 control sequence should be sent after a record that began with the start-of-record-l control sequence is received, while the acknowledge record 2 control sequence should be sent after a record that began with the start-of-record-2 control sequence is received. This assures the sender that the receiver has not lost a record. The last acknowledgment is always sent in response to an inquiry.

The repeat last record (error) control sequence is sent by a receiving terminal if it receives a block of data that is in error. This sequence notifies the transmitting terminal that it should repeat the transmission of the last record.

The end-of-transmission control sequence is sent by the transmitting terminal after it has sent the last record of a message. This indicates that the message has been sent completely. A receiving terminal answers the end-of-transmission control sequence by sending back an end-of-transmission control sequence, thereby notifying the transmitting terminal that the receiving terminal has received the full message. After the transmission of these two end-of-transmission control sequences, the two terminals return to synchronize mode of operation and exchange end-of-file idle sequence (handshake).

The telephone control sequence can be sent by either terminal and indicates that the terminal operator desires voice communication, via the handset, with the other terminal operator.

Synchronize Mode — STR

The synchronize mode (entered by a synchronize IOCC, with bit 11 = 1) provides a means of synchronizing the transmitting and receiving terminals to ensure the proper recognition of data bits and characters as they are transmitted between terminals. The synchronize mode consists of the transmission of a series of idle characters for 1.25 seconds, followed by a control sequence and then turning around and listening for a similar series of characters from the other terminal for 3 seconds. The time intervals for transmit (1.25 seconds) and receive (3 seconds) are controlled by timers in the adapter. The timers are under control of the program. The character used in the synchronization sequence is called an idle character.


Control Sequence Control Character Sequence
Leader
Character
Trailer
Character
End of IDLE (EOI)* CL 1 IDLE
Inquiry (Synchronized?)* TL INQ
Acknowledge (Synchronized) CL ACK 2
Telephone Sequence* CL TEL
Acknowledge Telephone* CL TEL
Start of Record 1 (SOR 1)
1st or odd numbered record
TL SOR 1
Start of Record 2 (SOR 2)
2nd or even numbered record
TL SOR 2
End of Transmittal Record (EOTR) TL LRC
Acknowledge Record 1 CL ACK 1
Acknowledge Record 2 CL ACK 2
Repeat Last Record (ERROR) CL ERR
Intermediate LRC** GM LRC
End of Transmission (EOT)* CL EOT
Acknowledge EOT* CL EOT
* These sequences are always preceded by a 1.25 second transmission of IDLE characters.
**This sequence may be required on some terminals i.e. 1013, 7701, 7702

Figure 74. Control Sequences

At the end of the 1.25-second transmission time, the transmitting terminal sends an end-of-idle control sequence — a control leader (CL) followed by an idle character (Figure 73). This control sequence signals the receiving (remote) terminal to change from receive mode to transmit mode. When the turnaround is completed (200 ms for two-wire half-duplex) the remote terminal transmits the idle character for 1.25 seconds. At the end of this time the remote terminal sends the end-of-idle sequence. If neither terminal has a message to transmit, the synchronization sequence continues.

Transmit Mode — STR

When a terminal has a message to transmit, that terminal sends 1.25 seconds of idle characters (caused by a synchronize IOCC, with bit 11 = 1) followed by the inquiry sequence. This sequence informs the remote terminal that a message is about to be transmitted. The remote terminal, if it is in synchronization and is ready to receive, sends an acknowledge control sequence (ACK2). On receipt of the acknowledge sequence, the transmitting terminal transmits its message.

The first two characters of a message are the start-of-record-1 sequence. This sequence is preceded by one or more idle characters. This sequence is followed by the message data characters for this record. Some terminals may use or require an intermediate block check. (This sequence is GM-LRC.) At the end of the record, the end-of-transmittal-record (EOTR) sequence is sent. This sequence consists of a TL character and a longitudinal redundancy check (LRC) character. Two functions are performed by this sequence: it indicates the end of the record, and provides (via the LRC character) the receiving terminal with a method of checking for a complete message. The receiving terminal acknowledges the EOTR by sending the acknowledge 1 or 2 sequence (if LRC compares) or by the error sequence (if LRC does not compare).

Messages which contain more than one record indicate the start of the second record by sending a start-of-record-2 sequence. The start-of-record-1 sequence is used each time an odd-numbered record is transmitted, and the start-of-record-2 sequence is used each time an even-numbered record is transmitted. The use of the two different start-of-record sequences enables detection of lost or duplicated data records from a terminal.

When the receiving terminal has acknowledged the correct receipt of the last record of a message, the transmitting terminal sends the end-of-transmission sequence. This sequence consists of a CL character and an end-of-transmission (EOT) character. The receiving terminal acknowledges the EOT sequence by returning the same sequence. The terminals, if so programmed, return to the synchronize mode.


Receive Mode — STR

In the receive mode, the adapter accepts data from other line devices and transfers it to the 1130 core storage. Prior to the transfer of data, the transmitting and receiving terminals must be synchronized.

In the receive mode, the adapter compares the incoming data to the character in the idle register. After at least one idle character has been recognized, the first non-idle character detected and all subsequent characters including idles are transferred into core storage. Idle characters and control sequences are not included in the LRC. When the transmitting terminal signals the end of a record, the 1130 program checks the transmitted LRC character with the one compiled from the received record. If the two LRC characters are the same, the 1130 program generates the appropriate acknowledgment, which is then sent from the adapter to the transmitting terminal. If the LRC characters are not the same, the 1130 program responds with an error sequence which is then sent from the adapter to the transmitting terminal. Normally, the 1130 program requests that the previous record be transmitted again. The number of transmission attempts is controlled by the programmer and may vary.


Special Programming

Special programming techniques are required in STR when an 1130 is used to communicate with a hardware device such as a 1013, 1009, or 7702. The special technique is required when either a 201 Data Set or an IBM 3977 Modem is used in a two-wire operation. No idles are received from these devices before the control leader (CL) or transmit leader (TL). Since the 1130 SCA requires at least one recognizable character before interrupting the CPU, the following special technique should be used:

  1. If the 1130 is the slave, it will be receiving records. After writing the acknowledgment character (ACK 1, ACK 2, or ERR), the program should load the sync/idle register with the TL. Since the TL is now the recognizable character, it is not loaded into the buffer for the CPU to read. The first character which interrupts the CPU is the trailer. The program must indicate to itself that the TL has already been received. This should be done when the first read interrupt occurs. If the 1130 times out, the remote station may send a message beginning with a TL or it may begin "handshaking" beginning with an idle character. To cope with either possibility, after a time-out, the 1130 program loads the sync register with a TL, and if another time-out occurs, the sync register is then loaded with an idle character. Once character phase is reestablished, the alternating of TL or idle characters ceases.
  2. If the 1130 is the master, it is sending records. After writing an INQ, the LRC character of an EOTR, or the last character of an abort sequence (idle), the program should load the sync/idle register with the CL. Since the CL is now the recognizable character, it is not loaded into the buffer for the CPU to read. The first character which interrupts the CPU is again the trailer. The program must indicate to itself that the CL has already been received. This can be done either at the time the sync/idle register is loaded with the CL or when the first read interrupt occurs.
    For both cases (1 and 2), the sync/idle register should be reloaded with the idle character prior to each transmission. An idle character should also remain in the sync/idle register after the program writes the idle of an end-of-idle sequence, or the TEL character, or the EOT character.
    Since the above technique works for all data sets and STR devices, it is recommended that it be followed.

Binary Synchronous Communications (BSC) Operation

In binary synchronous operation the receiving terminal's ability to interpret the data it receives is the prime consideration in selecting the code to use for communication.

A variety of codes for communication is available. The user may select any code of six, seven, or eight bits. IBM programming systems for the 1130 use the extended binary-coded-decimal interchange code (EBCDIC) communication control characters for all BSC operations. Figure 75 shows the control characters and Figure 76 shows the sequences in which they are used. In full-transparent text, control character recognition should be handled by a special procedure, thus making it possible to have data with the same configuration as control characters. All characters are transferred to core storage in the CPU for program interpretation. (Refer to IBM 1130 Synchronous Communications Adapter Subroutines, Order No. GC26-3706, for information concerning terminals and character codes supported.)

In the selection of a code, care must be taken in selecting the proper SYN character. If only two characters are used for synchronization, the first bit of the SYN character must be 0. A minimum of two characters are required for character-phase synchronization. The first bit of the character must be 0. The bit configuration must not be a repeating bit pattern (that is, the first of each character must be recognizable).

If the data set uses business machine clocking, several preceding characters must be transmitted to establish bit phase in the data set before the SYN characters mentioned above can be transmitted. These characters can be of the same bit configuration as the character-phase SYN character. The prime requirement for the characters used to establish bit phase is that the total line transitions must be a minimum of 16 before the data set is ready to accept the SYN characters for character phase.

Character Bit Configuration Meaning
0 1 2 3 4 5 6 7 Hex
SYN 0 0 1 1 0 0 1 0 32 Synchronous Idle
DLE 0 0 0 1 0 0 0 0 10 Data Link Escape
ENQ 0 0 1 0 1 1 0 1 2D Enquiry
SOH 0 0 0 0 0 0 0 1 01 Start of Heading
STX 0 0 0 0 0 0 1 0 02 Start of Text
ETB 0 0 1 0 0 1 1 0 26 End of Transmission Block
ETX 0 0 0 0 0 0 1 1 03 End of Text
EOT 0 0 1 1 0 1 1 1 37 End of Transmission
ITB 0 0 0 1 1 1 1 1 1F End of Intermediate Block
NAK 0 0 1 1 1 1 0 1 3D Negative Acknowledgement
*ACK 0 0 1 1 1 0 0 0 0 70 Positive Acknowledgement
(even record)
*ACK 1 0 1 1 0 0 0 0 1 61 Positive Acknowledgement
(odd record)
*RVI 0 1 1 1 1 1 0 0 7C Reverse Interrupt
*WACK 0 1 1 0 1 0 1 1 6B Wait Before Transmit
Positive Acknowledgement
PAD 1 1 1 1 1 1 1 1 FF Transmission Trailer
*Control characters when preceded by DLE

Figure 75. Binary Synchronous EBCDIC Control Characters



Characters Meaning
ENQ Enquiry
SOH Start of Heading
STX Start of Text
DLE STX Start of Transparent Text
ETB CRC-16* End of Block
DLE ETB CRC-16 End of Transparent Block
ETX CRC-16 End of Text
DLE ETX CRC-16 End of Transparent Text
DLE ACK 1 Acknowledgement of Odd Record
DLE ACK 0 Acknowledgement of Even Record
NAK Negative Acknowledgement
EOT End of Transmission
DLE EOT Disconnect Signal
SYN SYN Synchronous Idle (Normal)
DLE SYN Synchronous Idle (Transparent Text)
ITB CRC-16 End of Intermediate Block
DLE ITB CRC-16 End of Intermediate Transparent Block
DLE WACK Wait Before Transmit Positive
Acknowledgement
DLE RVI Reverse Interrupt
STX ENQ Temporary Text Delay
DLE DLE Data DLE in Transparent Mode
*CRC-16 is a 16-bit cyclic check character accumulated
from text and heading data.

Figure 76. Binary Synchronous Control Sequences


Control Operation — Binary Synchronous

The binary synchronous communications control procedures are generally independent of the transmission code. Any code having a fixed number of bits (six, seven, or eight) per character may be used if the ten control characters are set aside and a proper choice is made for the synchronous idle character. The EBCDIC control sequences are presented in this manual (Figure 75).

The control sequences are initiated by the 1130 program and transmitted to the remote terminal as data. The remote terminal then has the responsibility of recognizing the control sequences and responding appropriately.

All operations of the adapter are controlled by the 1130 program. The program places the adapter in either the synchronize (transmit) or the receive mode. In addition the program must initially store the synchronous idle (SYN) character in the sync/idle register. The program also accumulates the block check character (CRC-16), which is transmitted at the end of each record. Because the CRC is 16 bits long, two 8-bit characters must be transmitted and received.

In BSC, data may be transmitted in two modes: normal (EBCDIC) text and full-transparent text. In normal text mode, data may not have the same bit configuration as any control character. In full-transparent text, data may contain any bit configuration since control character recognition is handled by a special procedure. Full-transparent text is quite useful in transmitting machine language and other codes that may contain control characters.

In full-transparent mode, the DLE STX sequence is a special sequence that is transmitted prior to transmitting full-transparent text. When a receiving terminal receives this sequence it will stop checking for control characters and treat all subsequent characters as transparent text. The only control character that is recognized is another DLE character. The detection of another DLE character switches the mode back to normal text mode, and the receiving terminal will start checking for control characters. If the next character is DLE or SYN the receiving program will treat the character as data or as synchronous idle and will return to the transparent mode. Therefore, in full-transparent text mode, all control characters, including SYN, must be preceded by the DLE character to be recognized by the receiving terminal. In full-transparent mode the program must store the DLE character in the sync/idle register. The SYN character must be stored after leaving full-transparent text mode.

Line Turnaround

When a terminal wishes to transmit, it sends two SYN characters followed by the ENQ character. Then the terminal goes to the receive mode and waits for an acknowledgment from the receiving terminal. The receiving terminal detects the ENQ character as a request from the transmitting terminal, goes to the transmit mode, and replies with a positive acknowledgment (ACK0) if it is ready to receive. When the transmitting terminal receives the positive acknowledgment, it may start to transmit its record. If the receiving terminal is not ready to receive, it should respond with the NAK character (negative acknowledgment). If the terminal is unable to respond, the transmitting terminal will time out in 3 seconds.

Several of the control characters when detected by the program should cause line turnaround; that is, the transmitting terminal switches to the receive mode and the receiving terminal switches to the synchronize (transmit) mode.

Within the program, the end-of-block and the end-of-text (ETB and ETX) characters (when transmitting without checking), also cause line turnaround. IBM subroutines always use the block check character. The acknowledgments alternate: ACK1 for the first record and all succeeding odd records, and ACK0 for the second record and all succeeding even records. If the block check character is used, the line turnaround follows it. When a station is through transmitting, it may relinquish its right to transmit by sending the end-of-transmission (EOT) character. The EOT character does not require an acknowledgment. The right to transmit reverts back to the master station or to contention if a master station is not designated.

Multi-Point Operation

In multi-point, centralized operation, IBM programming systems include subroutines that permit the 1130 to operate only as a slave station. Programs to support noncentralized operation must be supplied by the user. A slave station is one that may respond to a call from the control (master) station but cannot initiate the call. Initialization is performed when the control station sends polling or selection addresses. A particular polling address gives a unique station on the line an opportunity to transmit to the control station. The polled station responds with a positive response (data transmission) or a negative response (EOT). Selection addresses are used to request a particular station to receive data transmission. A selected station responds with its status, ready to receive (ACK0) or not ready to receive (NAK).

A nonselected terminal should restart the timers and reset character phase on recognition of all turnaround sequences seen on the line.

In noncentralized operation, the operation is similar to centralized operation except the selected station (after being polled) must respond with its address and the address of the station to which it wishes to transmit. The selected station must reply with its address and a positive acknowledgment if it is ready to receive or a negative acknowledgment if it cannot receive.

Receive Mode — Binary Synchronous

In the receive mode, the adapter accepts data from the transmission line and transfers it to the 1130 core storage. Prior to the transfer of data, the adapter must be synchronized with the transmitting terminal. An initiate read command (110) with all modifier bits (8-15) set to 0 places the adapter in a receive mode.

In the receive mode, the adapter compares the incoming data to the character in the sync/idle register. After at least two SYN characters have been recognized, the first non-SYN character detected and all subsequent characters including SYN characters are transferred to core storage. The receive mode is terminated by the program when it detects a valid turnaround sequence.

For a slave station, if a receive time-out occurs, an end operation command should be used to reset the clock and character phase. The slave should issue an initiate read command immediately after the end operation command. If a receive time-out occurs, the master should issue an initiate write command to send ENQ.

Data Transmission — Binary Synchronous

Data sets (with business machine clocking) require a minimum of 16 line transitions to establish bit phase. The IBM-written program uses the normal SYN character (hexadecimal 32) for this. However, any character may be used. The 16 line transitions must precede the two SYN characters used to establish character phase in the SCA adapter. If data-set clocking is utilized, these preceding line transitions are not required.

In full-duplex operation, the SYN characters must be preceded by a pad character. The pad character cannot be another SYN character, but can be a marking line character (hexadecimal FF).

When a terminal has a message to transmit, the terminal sends the synchronous idle sequence followed by the enquiry control character. The enquiry character informs the remote terminal that a message is about to be transmitted. The remote terminal, if it is ready, sends the SYN characters and acknowledges by sending the acknowledge control sequence (DLE ACK0). Upon receipt of the acknowledge control sequence, the transmitting terminal transmits its message. The entire message, including control characters and check characters, is generated and transmitted from core storage under control of the stored program in the CPU.

Synchronize Mode — Binary Synchronous

The synchronize mode in binary synchronous communication is a transmit mode which allows a timeout to occur if the transmission is longer than 1.25 seconds. The program must insert the synchronous idle sequence after this timeout to ensure that the receiving terminal remains synchronized. Data transmission may continue after the synchronous idle sequence. The receiving terminal will time out if it does not receive the synchronous idle sequence within 3 seconds. A control command (100) with bit 11 set to 1 places the adapter in the synchronize mode.

Transmit Mode — Binary Synchronous

The transmit mode may be used in binary synchronous operation in lieu of the synchronize mode where a time-out is not required or desired. An initiate write command (101) with bit 9 set to 0 places the adapter in the transmit mode.

Special Programming

Most binary synchronous communications equipment with which the 1130 communicates generates block check characters (CRC-16) and expects block check characters following each line turnaround character. For this reason, the 1130 must generate and transmit these characters any time it communicates with such equipment. The block check characters must be accumulated under program control in the 1130.

The block check characters are formulated based upon the division algorithm for polynomials over the field of integers modulo two. In this field, addition and multiplication are performed according to the following rules:

Addition (Exclusive OR)   Multiplication
1 + 1 = 0   1 ⋅ 1 = 1
0 + 0 = 0   0 ⋅ 0 = 0
0 + 1 = 1   0 ⋅ 1 = 0
1 + 0 = 1   1 ⋅ 0 = 0

Operating under these rules, addition and subtraction are the same; in other words, a + b = a - b.

The block check characters are formed as a 16-bit remainder [R (x)] from the polynomial division:


B(x) ⋅ x16
-----------------------
x16 + x15 + x2 + 1

where B(x) = bnxn+bn-1xn-1 + ... b1x1 + b0x0.

The following equations illustrate the computation of the block-check characters for the two-character transmission G4:

Bits as transmitted: 1100 0111 1111 0100


B(x) = x15 + x14 + 0x13 + 0x12 + 0x11 + x10 + x9 + x8 + x7 + x6 + x5 + x4 + 0x3 + x2 + 0x + 0


B(x) ⋅ x16 = x31 + x30 + 0x29 + 0x28 + 0x27 + x26 + x25 + x24 + x23 + x22 + x21 + x20 + 0x19 + x18 + 0x17 + 0x16 + 0x15 + 0x14 + 0x13 + 0x12 + 0x11 + 0x10 + 0x9 + 0x8 + 0x7 + 0x6 + 0x5 + 0x4 + 0x3 + 0x2 + 0x + 0


B(x) ⋅ x16
------------------------
x16 + x15 + x2 + 1
= x15 + x10 + x8 + x6 + x4 + x3 + x
+ 1 with a remainder R(x)

R(x) = 0x15 + 0x14 + 0x13 + x12 + 0x11 + 0x10 + 0x9 + 0x8 + 0x7 + 0x6 + x5 + x4 + 0x3 + x2 + x + 1


Block check character = 0001 0000 0011 0111

This 16-bit block check character is transmitted as two 8-bit characters by the transmitting station and compared at the receiving station with block check characters accumulated by the same algorithm. If the block check characters are equal, the transmission is acknowledged as correct by the receiving station.

Characters are included in the block check accumulation under the following rules. In nontransparent mode:

  1. The first SOH or STX character clears the count and is not included in the accumulation.
  2. All other characters after the initial SOH or STX are included in the block check character accumulation, except SYN.
  3. An ITB character encountered in the message is included in the accumulation. The block check characters are transmitted (or received and compared) immediately following the ITB character. The block check characters are cleared and a new accumulation starts with the next non-SYN character received.
  4. An end of block line turnaround character (ETB or ETX) is included in the block check character summation. The block check characters are transmitted (or received and compared) immediately following the ETB or ETX. The block check summation is ended by either of these line turn around characters and will not resume until a new SOH or STX character is encountered.

In transparent mode:

  1. The block check summation is initiated by the first appearance of an SOH or an XSTX character. This character clears the summation and is not included in the summation.
  2. All characters transmitted after the initial SOH or XSTX are included in the block check summation up to and including the first end of block line turnaround character (XETB, XETX in transparent blocks, ETB or ETX in nontransparent blocks). An XSTX following an XITB is included as the first character of the summation following clearing of the summation after checking is performed.
  3. The idle character (XSYN) is not included in the block check summation.
  4. The DLE character used to designate that the control character or transparent DLE character transmitted is to be used as a control character is not included in the block check summation except for the DLE STX sequence following heading information, ITB, or XITB.

PROGRAMMING

All adapter operations are programmed using the 1130 XIO instruction (see execute I/O description in this manual). The effective address position of the XIO instruction specifies the address of the two-word IOCC which is required for the desired operation.

The adapter interrupts the 1130 system program on interrupt level 1. Bit position 1 of this interrupt level status word (ILSW) indicates that the interrupting device is the adapter. The program then senses the device status word (DSW).

Figure 77.  Device Status Word
Figure 77. Device Status Word

The DSW is generated by the adapter to indicate the cause of the interrupt (Figure 77). The DSW bit positions indicate the following conditions:

Bit 0
The adapter is in receive mode (or diagnostic mode) and the buffer register in the adapter contains a data character which should be transferred into the 1130 core storage.
Bit 1
The adapter is in transmit mode (or diagnostic mode) and requires a data character from the 1130 core storage for transmission.
Bit 2
This bit indicates an error condition: data overrun or character gap.
Data overrun indicates that a character was still in the buffer when another character came, either from the transmission line (receive mode) or from core storage (transmit mode). This condition results in a loss of data. In the transmit mode, data overrun is the result of a program sending another character to the adapter without an interrupt request from the adapter. In the receive mode, this condition is the result of a program operating too slow; that is, a character is received from the transmission line before the preceding character has been transferred to core storage (interrupt not yet serviced).
Character gap indicates that the data characters are being received by the buffer too slowly for correct adapter operation. In the transmit mode, the program is operating too slowly. (Note: The adapter automatically transmits the character in the sync/idle register.) In the receive mode, the program requested another character from the adapter without an interrupt request from the adapter.
Bit 3
In STR this bit indicates the end of the 1.25-second timeout for transmission of idle characters, or the end of the three second listening time for synchronization. In BSC this bit indicates it is time to insert the synchronous idle sequence in synchronize mode, or a receive time-out occurred in the receive mode or a sync insertion is required in transparent mode.
Bit 4
This bit indicates that the data-set phone is ringing. Bit 4 is used only if the auto-answer feature is in the data set.
Bit 5
This bit indicates that the adapter is in either the receive or transmit mode.
Bit 6
This bit indicates that the adapter has been enabled for an auto answer request interrupt. (See Bit 4.)
Bit 7
This bit indicates that the data set is connected and ready to receive, synchronize, or transmit data.
Bit 8
This bit is used with two-wire half-duplex STR systems only. It indicates that the adapter is in the "slave" mode. In slave mode the adapter transmits the normal acknowledge responses but does not transmit data records. Receive and transmit clocks are tied together. The transmit clock is corrected with the receive clock when correction is required.

I/O Control Commands (IOCC)

The adapter is addressed by the five-bit (bits 0 through 4) device (area) code in the IOCC. This code is 01010.


Write (001)

SCA IOCC Write command

A write command without a modifier bit instructs the 1130 to transfer the contents of the specified core storage address to the adapter buffer. The adapter then serializes the contents of the buffer register onto the transmission line.

If modifier bit 13 is set, this command is used to set the sync/idle register. The 1130 transfers the data to the sync/idle register in the adapter. The idle character is transmitted during the synchronize mode or when the adapter is in transmit mode and has not received a data character for transmission.

Modifier bit 14 turns on the audible alarm trigger in the adapter.

Modifier bit 15 turns off the audible alarm trigger.


Read (010)

SCA IOCC Read command

The read command instructs the 1130 to transfer the contents of the adapter buffer to the core storage location specified in the address portion of the command. Modifier bits 14 and 15 must be 0's in application programs. When on, they are used for reading diagnostic words.


Control (100)

SCA IOCC Control command

The control command is always used with a modifier bit. This command causes the adapter to accomplish the functions specified by the modifier.

Modifier bit 8, when set to 1, enables the adapter for auto answer operation. Auto answer allows the adapter to interrupt the 1130 program in response to a telephone ring from the remote terminal.

Modifier bit 9, when set to 1, disables the auto answer operation and does not allow a telephone ring from the remote terminal to interrupt the 1130 program.

Modifier bit 10 reverses the status of the timers from run to inhibit or from inhibit to run.

Modifier bit 11 sets the adapter to the synchronize mode. This is used to establish and maintain synchronization in the STR mode with minimum program interruption. Idles are transmitted without the program being interrupted until transmit time-out occurs.

In binary synchronous mode, modifier bit 11 allows the adapter to transmit in the synchronize mode. Write responses occur normally. A transmission longer than 1.25 seconds causes a time-out interrupt. The program must transmit the synchronous idle sequence before continuing to transmit data. The synchronous idle sequence is the only synchronization necessary in BSC. This usually consists of two sync characters.

If the SCA is not already in transmit mode when this command is given, a turnaround occurs. The turnaround, with a 1 in position 0, 1, 3, or 4 of the address word in the IOCC, resets the corresponding position of the DSW.

The on condition of modifier bit 12 places the adapter in a diagnostic condition. Bit 12 should be off for all application programs. Because of the short time between interrupts in this condition, the diagnostic program should be run alone.

Modifier bit 13 is the end operation command. This command resets the adapter regardless of the mode of operation. If the adapter is in the transmit mode, the reset is delayed until a character gap of one character is detected. This allows the last character to get through the data set before the adapter is reset. It then resets the adapter and also resets the timers used in the synchronization mode and disconnects the adapter from the communication line if a switched network is used. In binary synchronous mode, this command should be issued after a receive time-out to reset the clock.

Modifier bit 14 is used to set the adapter for a six-bit character frame. Setting bit 14 automatically resets the seven-bit character mode.

Modifier bit 15 is used to set the adapter for a seven-bit character frame. Setting bit 15 automatically resets the six-bit character mode.

Both frame size modes are reset when the adapter leaves both the receive and transmit mode. Thus it becomes necessary to reenter the proper mode after each line turnaround. Attempting to set both bit 14 and bit 15 with the same instruction is ambiguous and may result in an error.


Initiate Write (101)

SCA IOCC Initiate Write command

The initiate write command places the adapter in the transmit mode of operation.

If the SCA is not already in transmit mode when this command is given, a turnaround occurs. The turnaround, with a 1 in position 0, 1, 3, or 4 of the address word in the IOCC, resets the corresponding position of the DSW (i.e., read response, write response, timeout, or auto answer request). Initiate write with modifier bit 9 on resets all conditions in the adapter.


Initiate Read(110)

SCA IOCC Initiate Read command

The initiate read command places the adapter in the receive mode of operation.

An initiate read command with modifier bit 14 on sets the send/receive run trigger and places the adapter in slave mode operation for STR operation. This mode of operation is used with two-wire half-duplex systems. In the slave mode the adapter should not be programmed to transmit data records to the master. The only transmissions that the adapter will make are the normal responses to the inquiry from the master and the normal acknowledgments. The start-read command and a modifier bit 15 clears the send/receive run trigger and removes the adapter from slave mode operations. This clearing places the adapter in the master mode, which is used for the transmission of data.


Sense Device (111)

SCA IOCC Sense Device command

The sense device command instructs the 1130 to sense the device status word (DSW). The DSW is generated by the adapter to indicate the cause of the interrupt. The DSW for the adapter is shown in Figure 77.

Sense DSW with modifier bit 14 on will restart the timers. If the synchronous idle sequence is received while in BSC receive mode, the program should restart the timer. If the timer is not reset within 3 seconds, the adapter will cause a time-out interrupt. Sense DSW with modifier bit 15 on resets the device status word responses.

TIMING FOR SCA PROGRAMMING

In order to prevent an overrun on receive a character must be sent from the SCA buffer following a read response interrupt within the period shown in Figure 78. Also to prevent a character gap on transmission, a character must be written to the SCA buffer following a write response within the period shown in Figure 78.


Figure 78.  Transmission timing
Figure 78. Transmission Timing



But wait, there's MORE...

And there's LESS...

And there's the rest