Branch and Store Instruction Address Register
Organizational graphic tag to help group instructions

Mnemonic

 BSI

Short and Long format of instruction



Short-Format Description

For the short format of this instruction, an unconditional branch always occurs, and the address in the instruction-address register is stored at a specified core-storage location. The address stored is that of the instruction immediately following the location of the branch instruction (BSI). This address is stored at the location specified by the effective address generated as a result of execution of the branch instruction. The instruction-address register is then loaded with the generated effective address plus one. Consequently, the location of the next instruction that is executed starts at the word immediately following the location specified by the generated effective address. Pictorially, the operation is as follows:

The contents of the instruction address register are stored at the location specified by the effective address
The instruction address register is updated to the effective address plus one

Normal short format addressing applies to this instruction (refer to "Short Instruction Address Generation"). Notice that the address stored (the address from the instruction-address register) is that of the instruction located immediately after (in core storage) the branch-and-store-instruction- address-register instruction.




Long-Format Description

In the long format, this instruction operates in a manner similar to the long-format branch-or-skip-on-condition instruction (BSC). Two actions are conditional:

  1. Storing of the address contents of the instruction-address register
  2. Branching to the instruction at the location specified by the effective address plus one

The testable items are the same as those in the branch-or-skip-on-condition instruction:

Modifier Bit (When = 1)   Specifies Testing of
15   Overflow indicator off
14   Carry indicator off
13   Accumulator even
12   Accumulator plus (greater than zero)
11   Accumulator negative
10   Accumulator zero

If any one or more of the specified items is at the stated condition, the branch is not performed, and the contents of the instruction-address register are not stored. For example, if overflow-off is to be tested and the overflow indicator is off, the branch is not performed and the address is not stored.

On the other hand, if none of the testable items are at the stated condition (or if no condition is specified):

  1. The contents of the instruction-address register are stored at the location specified by the effective address.
  2. The next instruction executed is at the effective address plus one.

These two actions are done in the same manner as described for the short format of this instruction. Addressing is performed in the normal manner (refer to "Long Instruction Address Generation").

A branch-and-store-instruction-address-register instruction that specifies indirect addressing is forced by the CPU during initiation of interrupt action. In this case, the branch instruction is not in core storage but is forced into circuitry by the CPU. At the end of the interrupt subroutine, a branch-or-skip-on-condition instruction (BOSC) should be executed to return to the stored address. Instruction execution can then resume at the point at which the program was stopped when the interrupt originally occurred. (Refer to "I/O Interrupts" for further details.)


Indicators: For the short-instruction format, neither indicator (carry or overflow) is affected. In the long format, the overflow indicator is reset if tested. The carry indicator is not reset by testing. Contents of the accumulator are not changed by testing.


Examples

Branch and Store Instruction Address Register

Assembler Language Coding Hexadecimal Value Description of Instruction
Label   Operation   F T    
21 25
 
27 30
  32 33   35..40..
    BSI         DISP 40XX Store next sequential address in BSL at EA (I + DISP) and Branch to EA + 1
    BSI     1   DISP 41XX Store next sequential address in BSL at EA (XR1 + DISP) and Branch to EA + 1
    BSI     2   DISP 42XX Store next sequential address in BSL at EA (XR2 + DISP) and Branch to EA + 1
    BSI     3   DISP 43XX Store next sequential address in BSL at EA (XR3 + DISP) and Branch to EA + 1
    BSI   L     ADDR,COND 44*XXXXX If NO condition is true, store next sequential address in CSL at EA (Addr) and Branch to EA + 1
    BSI   L 1   ADDR,COND 45*XXXXX If NO condition is true, store next sequential address in CSL at EA (Addr + XR1) and Branch to EA + 1
    BSI   L 2   ADDR,COND 46*XXXXX If NO condition is true, store next sequential address in CSL at EA (Addr + XR2) and Branch to EA + 1
    BSI   L 3   ADDR,COND 47*XXXXX If NO condition is true, store next sequential address in CSL at EA (Addr + XR3) and Branch to EA + 1
    BSI   I     ADDR,COND 44*XXXXX If NO condition is true, store next sequential address in CSL at EA (V in CSL at Addr) and Branch to EA + 1
    BSI   I 1   ADDR,COND 45*XXXXX If NO condition is true, store next sequential address in CSL at EA (V in CSL at "Addr + XR1") and Branch to EA + 1
    BSI   I 2   ADDR,COND 46*XXXXX If NO condition is true, store next sequential address in CSL at EA (V in CSL at "Addr + XR2") and Branch to EA + 1
    BSI   I 3   ADDR,COND 47*XXXXX If NO condition is true, store next sequential address in CSL at EA (V in CSL at "Addr + XR3") and Branch to EA + 1

In the long format, if COND is not specified, the branch is always taken.

* This hexadecimal digit is determined by the testable items specified.



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