|BSC or BOSC|
For the short format of the instruction, the action taken as a result of execution of the instruction is one of the following:
The next word must be a short format instruction. Otherwise, when the skip occurs, the second word of a long-format instruction would be accessed, resulting in a programming error.
Whether the skip is taken is dependent upon what testable items are specified by the modifier bits in the instruction and the conditions of these testable items:
|Modifier Bit (When = 1)||Specifies Testing of|
|15||Overflow indicator off|
|14||Carry indicator off|
|12||Accumulator plus (greater than zero)|
If any specified testable item is at the stated condition, the skip is taken; if no specified testable item is at the stated condition, the skip is not taken.
For example, the carry-indicator-off and overflow-indicator-off conditions are to be tested (modifier bits 14 and 15 in the instruction are on). If either or both indicators (carry or overflow) are off, the skipped-to instruction is executed after the branch-or-skip-on-condition instruction. If both of the indicators are on, however, the next word is the instruction executed after the BSC instruction:
Examples of skipping for various combinations of specified testable items are shown in Figure 16. A skip occurs only if a specified testable item is at the stated condition -- for example, the carry indicator off. (The long format of this instruction, on the other hand, operates in exactly the opposite manner.)
Core storage is not explicitly addressed during execution of the branch-or-skip-on-condition instruction. Either the very next word becomes the next instruction, or the skip is taken to the second word.
The same testable items can be specified by the same modifier bits in the long-format of the branch-or-skip-on-condition instruction as in the short format of the instruction. With the long format, however, a branch occurs rather than a skip. The core storage location branched-to contains the next instruction to be executed. Any core-storage location can be addressed for branching. The branch, however, occurs only when none of the specified testable items are at the stated conditions. The branch is to the location specified by the effective address, which is formed in the usual manner (refer to "Long Instruction Address Generation"). If no condition is specified, the instruction performs an unconditional branch.
For example, the accumulator-zero and carry-indicator-off testable items are specified (modifier bits 10 and 14 are on). If the accumulator is not zero and if the carry indicator is on, a branch occurs. Otherwise, the next sequential instruction (located immediately after the branch-or-skip- on-condition instruction) is executed.
Examples of branching for various combinations of specified testable items are shown in Figure 16.
When the indirect-address bit (bit 8) is equal to 1, indirect addressing is specified. In this case, the branch-or-skip-on-condition instruction enables the program to return to a mainline program from a subroutine or interrupt routine. This is accomplished by making the effective address of the instruction identical to the effective address of a previously executed branch-and-store-instruction-address-register instruction.
Programming Note: For an overall description of interrupts refer to "I/O Interrupts". When an interrupt request has been detected by a priority level, an interrupt occurs. The interrupt action causes a forced CPU branch (and store instruction register) to an interrupt handling subroutine. During execution of the subroutine, all interrupt requests of equal or lower priority status are prevented from interrupting the subroutine. If a request for a higher priority interrupt is detected, however, the program (subroutine) is immediately interrupted again.
At the completion of servicing any level of interrupt, the priority-status of the highest level is reset. This reset permits lower priority requests that may have been temporarily prevented to be accepted again. (Requests that have been made are recorded and are initiated again.) The reset to the current priority level (made at the end of the subroutine) is effected through execution of a branch-or-skip-on-condition instruction in which bit 9 = 1. A branch-or-skip-on-condition instruction with bit 9 = 1 is called a branch out of interrupts. (The mnemonic is BOSC.)
But the branch on condition is still conditional (if conditions are specified when bit 9 = 1). Reset of the interrupt level occurs only if the branch or skip occurs. If the branch or skip does not occur, the interrupt level is not reset. Branching or skipping is dependent upon the format, the conditions tested, and the state of the conditions tested.
This programmed branch back from an interrupt subroutine should not be confused with a normal linkage from one routine to another in which bit 9 equals 0.
Indicators: The overflow indicator is reset when tested. The carry indicator is not reset when tested. Contents of the accumulator are not changed by testing.
Branch or Skip on Condition
|Assembler Language Coding||Hexadecimal Value||Description of Instruction|
|BSC||COND||48*X||Skip the next one-word instruction if ANY condition is sensed|
|BSC||L||ADDR,COND||4C*XXXXX||Branch to CSL at EA (Addr) on NO condition|
|BSC||L||1||ADDR,COND||4D*XXXXX||Branch to CSL at EA (Addr+XR1) on NO condition|
|BSC||L||2||ADDR,COND||4E*XXXXX||Branch to CSL at EA (Addr+XR2) on NO condition|
|BSC||L||3||ADDR,COND||4F*XXXXX||Branch to CSL at EA (Addr+XR3) on NO condition|
|BSC||I||ADDR,COND||4C*XXXXX||Branch to CSL at EA (V in CSL at Addr) on NO condition|
|BSC||I||1||ADDR,COND||4D*XXXXX||Branch to CSL at EA (V in CSL at "Addr+XR1") on NO condition|
|BSC||I||2||ADDR,COND||4E*XXXXX||Branch to CSL at EA (V in CSL at "Addr+XR2") on NO condition|
|BSC||I||3||ADDR,COND||4F*XXXXX||Branch to CSL at EA (V in CSL at "Addr+XR3") on NO condition|
A BOSC can be used in any of the above examples instead of a BSC.
IF COND is not specified:
|* This digit is determined by the desired condition(s) specified.|
But wait, there's MORE...